1. Field of the Invention
This invention relates generally to the field of digital data processing systems, and more specifically to an improved arrangement by which a unit of the data processing system obtains access to the system bus to interrupt the processor of the data processing system.
2. Description of the Prior Art
A digital data processing system generally includes three basic elements: a memory element, an input/output element, and a processor element all interconnected by one or more buses. The memory element stores information in addressable storage locations. This information includes both data and instructions for processing the data. The processor element causes information to be transferred between it and the memory element, interprets the incoming information as either data or instructions, and processes the data in accordance with the instructions. An input/output element also communicates with the memory element in order to transfer information into the system and to obtain the processed information from it. The input/output elements normally operate in accordance with control information supplied to it by the processor element. The input/output elements may include operator consoles, printers or teletypewriters, or may also include secondary memory storage units such as disk drives or tape drives.
When an event occurs in the input/output element, or to a lesser degree the memory element, the element "interrupts" the processor element to permit it to ascertain the nature of the event and to perform such operations as may be necessitated by the event. For example, when the input/output element finishes processing control information previously supplied to it by the processor element, the input/output element may "interrupt" the processor element. The processor may then execute certain interrupt service routines required for the particular element. The input/output element may also interrupt the processor element to indicate that it is available for use, or to facilitate immediate recognition by the processor of special conditions or errors.
As a specific example of an interrupt, consider the operation of retrieving the contents of a certain track from a storage disk in a secondary memory storage unit such as the one disclosed in the aforementioned U.S. Pat. No. 3,999,163. The processor first must have the disk drive locate the track whose contents are to be retrieved, that is, the processor must have the disk drive move the head to the desired track. To do this, it loads address information into certain address registers, in particular the Desired Track Sector Register and Desired Cylinder Address Register, in the drive through the drive's controller. The processor also loads a search command in the Function portion of a Control and Status Register and sets a Go bit. The drive then moves the read/write head to the desired track.
When the drive locates the desired track identified by the address registers, the drive transmits an ATTN attention signal to its controller, which then transmits an interrupt request signal to the processor. The processor, if it is in condition to be interrupted, may then transmit a signal to the controller granting the interrupt. Typically, a processor will not transmit an interrupt grant signal if it is currently executing an instruction, and it typically waits until the end of the execution cycle of the instruction before granting the interrupt. Some processors, such as the VAX 11/780 processor sold by Digital Equipment Corporation, determine an interrupt priority level (IPL) based on the operating status of the processor. The interrupt requests from the various units of the system are assigned to certain interrupt levels, and if the request has a higher level than the processor's current interrupt priority level, the interrupt grant signal will be transmitted.
At this point, the processor may not know which unit is requesting the interrupt or the location in memory of the interrupt service routine for the unit. This may be the case if the interrupt request signal does not uniquely identify the unit requesting the interrupt or the location of the interrupt service routine. The processor then must be apprised of the location in memory of the interrupt service routine to permit it to service the interrupt.
After the interrupting unit receives a interrupt grant signal from the processor granting the interrupt, it can transfer a "vector" to the processor, as is done in the PDP-11 systems sold by Digital Equipment Corporation. The "vector" is the address in memory of the beginning of the interrupt service routine.
Returning to the foregoing example of the transfer from the disk drive, when the processor starts executing the interrupt service routine, it may transmit a command to the disk drive to read the contents of the located track into a particular portion of the memory element. In processing the interrupt service routine, the processor loads registers in disk controller with the address in memory to which the track contents are to be transferred and identifying the number of words to be transferred. The processor also loads the control and status register in the drive with a transfer command and sets a "GO" bit. The drive, under the control of the controller, then reads the contents of the track and transfers them to the controller, which transfers them to the location in memory specified by the processor. After it has transferred the number of words requested by the processor, the controller can stop the transfer.
After the transfer is complete, the drive, through the controller, can again interrupt the processor so that it may verify that the transfer has been completed without error, or if any errors occurred, to permit the errors to be corrected.